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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8422004I
FEMTOCLOCKSTMLVCMOS/CRYSTAL-TOLVHSTL FREQUENCY SYNTHESIZER
FEATURES
* Four LVHSTL outputs (VOHmax = 1.2V) * Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input * Supports the following output frequencies: 212.5MHz, 187.5MHz, 159.375MHz, 156.25, 106.25MHz, 53.125MHz * VCO range: 560MHz - 680MHz * RMS phase jitter @ 212.5MHz, using a 26.5625MHz crystal (637kHz - 10MHz): 0.59ps (typical) * Power supply modes: Core/Output 3.3V/1.8V 2.5V/1.8V * -40C to 85C ambient operating temperature
GENERAL DESCRIPTION
The ICS8422004I is a 4 output LVHSTL Synthesizer optimized to generate Fibre Channel reference HiPerClockSTM clock frequencies and is a member of the HiPerClocksTM family of high performance clock solutions from ICS. Using a 26.5625MHz 18pF parallel resonant crystal, the following frequencies can be generated based on the 2 frequency select pins (F_SEL[1:0]): 212.5MHz, 187.5MHz, 159.375MHz, 156.25, 106.25MHz and 53.125MHz. The ICS8422004I uses ICS' 3rd generation low phase noise VCO technology and can achieve 1ps or lower typical rms phase jitter, easily meeting Fibre Channel jitter requirements. The ICS8422004I is packaged in a small 24-pin TSSOP package.
ICS
FREQUENCY SELECT FUNCTION TABLE
Input Frequency (MHz) 26.5625 26.5625 26.5625 26.5625 26.04166 23.4375 Inputs M Divider N Divider Value Value 24 3 24 24 24 24 24 4 6 12 4 3 M/N Divider Value 8 6 4 2 6 8 Output Frequency (MHz) 212.5 159.375 106.25 53.125 156.25 187.5
PIN ASSIGNMENT
nQ1 Q1 VDDO Q0 nQ0 MR nPLL_SEL nc VDDA F_SEL0 VDD F_SEL1 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 nQ2 Q2 VDDO Q3 nQ3 GND nc nXTAL_SEL TEST_CLK GND XTAL_IN XTAL_OUT
F_SEL1 F_SEL0 0 0 1 1 0 0 0 1 0 1 1 0
ICS8422004I
BLOCK DIAGRAM
F_SEL[1:0] Pulldown nPLL_SEL Pulldown TEST_CLK Pulldown
26.5625MHz
2
24-Lead TSSOP 4.40mm x 7.8mm x 0.92mm package body G Package Top View Q0
F_SEL[1:0] 0 0 /3 1 01 10 11 /4 /6 /12
1
nQ0 Q1 nQ1
XTAL_IN
OSC
XTAL_OUT nXTAL_SEL
Pulldown
0
Phase Detector
VCO
0
Q2 nQ2
M = 24 (fixed)
Q3 nQ3
MR
Pulldown
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 8422004AGI www.icst.com/products/hiperclocks.html REV. A MARCH 29, 2005
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8422004I
FEMTOCLOCKSTMLVCMOS/CRYSTAL-TOLVHSTL FREQUENCY SYNTHESIZER
Type Description Differential output pair. LVHSTL interface levels. Output supply pins. Differential output pair. LVHSTL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inver ted outputs nQx Pulldown to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Selects between the PLL and TEST_CLK as input to the dividers. When Pulldown LOW, selects PLL (PLL Enable). When HIGH, deselects the reference clock (PLL Bypass). LVCMOS/LVTTL interface levels. No connect. Analog supply pin. Pulldown Frequency select pins. LVCMOS/LVTTL interface levels. Core supply pin. Parallel resonant cr ystal interface. XTAL_OUT is the output, XTAL_IN is the input. Power supply ground. Pulldown LVCMOS/LVTTL clock input. Selects between cr ystal or TEST_CLK inputs as the the PLL Reference Pulldown source. Selects XTAL inputs when LOW. Selects TEST_CLK when HIGH. LVCMOS/LVTTL interface levels. Differential output pair. LVHSTL interface levels. Differential output pair. LVHSTL interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1, 2 3, 22 4, 5 6 Name nQ1, Q1 VDDO Q0, nQ0 MR Output Power Ouput Input
7 8, 18 9 10, 12 11 13, 14 15, 19 16 17 20, 21 23, 24
nPLL_SEL nc VDDA F_SEL0, F_SEL1 VDD XTAL_OUT, XTAL_IN GND TEST_CLK nXTAL_SEL nQ3, Q3 Q2, nQ2
Input Unused Power Input Power Input Power Input Input Output Output
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLDOWN Parameter Input Capacitance Input Pulldown Resistor Test Conditions Minimum Typical 4 51 Maximum Units pF k
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REV. A MARCH 29, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8422004I
FEMTOCLOCKSTMLVCMOS/CRYSTAL-TOLVHSTL FREQUENCY SYNTHESIZER
4.6V -0.5V to VDD + 0.5V 50mA 100mA 70C/W (0 mps) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V5%, VDDO = 1.8V0.2V, TA = -40C TO 85C
Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current No Load Test Conditions Minimum 3.135 3.135 3.135 Typical 3.3 3.3 3.3 90 10 0 Maximum 3.465 3.465 3.465 Units V V V mA mA mA
TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 2.5V5%, VDDO = 1.8V0.2V, TA = -40C TO 85C
Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current No Load Test Conditions Minimum 2.375 2.375 2.375 Typical 2.5 2.5 2.5 80 10 0 Maximum 2.625 2.625 2.625 Units V V V mA mA mA
TABLE 3C. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V5% OR 2.5V5%, VDDO = 1.8V0.2V,
TA = -40C TO 85C
Symbol VIH VIL IIH Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current TEST_CLK, MR, F_SEL0, F_SEL1, nPLL_SEL, nXTAL_SEL TEST_CLK, MR, F_SEL0, F_SEL1, nPLL_SEL, nXTAL_SEL Test Conditions VDD = 3.3V VDD = 2.5V VDD = 3.3V VDD = 2.5V VDD = VIN = 3.465V or 2.5V VDD = 3.465V or 2.5V, VIN = 0V -150 Minimum Typical 2 1.7 -0.3 -0.3 Maximum VDD + 0.3 VDD + 0.3 0.8 0.7 150 Units V V V V A
IIL
8422004AGI
A
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REV. A MARCH 29, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8422004I
FEMTOCLOCKSTMLVCMOS/CRYSTAL-TOLVHSTL FREQUENCY SYNTHESIZER
Test Conditions Minimum 1.0 0 40 0.6 Typical Maximum 1.2 0.4 60 1.1 Units V V % V
TABLE 3D. LVHSTL DC CHARACTERISTICS, VDD = VDDA = 3.3V5%, VDDO = 1.8V0.2V, TA = -40C TO 85C
Symbol VOH VOL VOX Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Output Crossover Voltage; NOTE 2
Peak-to-Peak Output Voltage Swing VSWING NOTE 1: Outputs terminated with 50 to ground. NOTE 2: Defined with respect to output voltage swing at a given condition.
TABLE 3E. LVHSTL DC CHARACTERISTICS, VDD = VDDA = 2.5V5%, VDDO = 1.8V0.2V, TA = -40C TO 85C
Symbol VOH VOL VOX Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Output Crossover Voltage; NOTE 2 40 0.9 Test Conditions Minimum 1.0 0.235 60 Typical Maximum 1.2 Units V V % V
Peak-to-Peak Output Voltage Swing VSWING NOTE 1: Outputs terminated with 50 to ground. NOTE 2: Defined with respect to output voltage swing at a given condition.
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level NOTE: Characterized using an 18pF parallel resonant crystal. 23.33 Test Conditions Minimum Typical 26.5625 Maximum 28.33 50 7 1 Units MHz pF mW Fundamental
8422004AGI
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REV. A MARCH 29, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8422004I
FEMTOCLOCKSTMLVCMOS/CRYSTAL-TOLVHSTL FREQUENCY SYNTHESIZER
Test Conditions F_SEL[1:0] = 00 F_SEL[1:0] = 01 F_SEL[1:0] = 10 F_SEL[1:0] = 11 Minimum 186.67 140 93.33 46.67 TBD 212.5MHz, (637kHz - 10MHz) 187.5MHz, (637kHz - 10MHz) 0.59 0.53 0.56 0.50 0.56 0.66 410 Typical Maximum 226.66 170 113.33 56.66 Units MHz MHz MHz MHz ps ps ps ps ps ps ps ps %
TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = 3.3V5%, VDDO = 1.8V0.2V, TA = -40C TO 85C
Symbol Parameter
fOUT
Output Frequency
tsk(o)
Output Skew; NOTE 1, 3
tjit(O)
RMS Phase Jitter (Random); NOTE 2
159.375MHz, (637kHz - 10MHz) 156.25MHz, (1.875MHz - 20MHz) 106.25MHz, (1.875MHz - 20MHz) 53.125MHz, (637kHz - 10MHz)
tR / tF
Output Rise/Fall Time
20% to 80%
odc Output Duty Cycle 50 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: Please refer to the Phase Noise Plot. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = 2.5V5%, VDDO = 1.8V0.2V, TA = -40C TO 85C
Symbol Parameter Test Conditions F_SEL[1:0] = 00 fOUT Output Frequency F_SEL[1:0] = 01 F_SEL[1:0] = 10 F_SEL[1:0] = 11 Minimum 186.67 140 93.33 46.67 TBD 212.5MHz, (637kHz - 10MHz) 187.5MHz, (637kHz - 10MHz) RMS Phase Jitter (Random); NOTE 2 159.375MHz, (637kHz - 10MHz) 156.25MHz, (1.875MHz - 20MHz) 106.25MHz, (1.875MHz - 20MHz) 53.125MHz, (637kHz - 10MHz) tR / tF Output Rise/Fall Time 20% to 80% 0.60 0.72 0.64 0.50 0.55 0.68 380 Typical Maximum 226.66 170 113.33 56.66 Units MHz MHz MHz MHz ps ps ps ps ps ps ps ps %
tsk(o)
Output Skew; NOTE 1, 3
tjit(O)
odc Output Duty Cycle 50 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: Please refer to the Phase Noise Plot. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
8422004AGI
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REV. A MARCH 29, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8422004I
FEMTOCLOCKSTMLVCMOS/CRYSTAL-TOLVHSTL FREQUENCY SYNTHESIZER
TYPICAL PHASE NOISE AT 212.5MHZ
0 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1M 10M 100M
Fibre Channel Jitter Filter
-10
212.5MHz
RMS Phase Jitter (Random) 637kHz to 10MHz = 0.59ps (typical)
NOISE POWER dBc Hz
Raw Phase Noise Data
Phase Noise Result by adding Fibre Channel Filter to raw data OFFSET FREQUENCY (HZ)
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8422004AGI
REV. A MARCH 29, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8422004I
FEMTOCLOCKSTMLVCMOS/CRYSTAL-TOLVHSTL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
3.3V5% 1.8V0.2V 2.5V5% 1.8V0.2V
VDD, VDDA VDDO
Qx
SCOPE
VDD, VDDA VDDO
Qx
SCOPE
HSTL
GND
nQx
HSTL
GND
nQx
0V
0V
LVHSTL 3.3V/1.8V OUTPUT LOAD AC TEST CIRCUIT
LVHSTL 2.5V/1.8V OUTPUT LOAD AC TEST CIRCUIT
nQx 80% Qx nQy Qy
tsk(o)
80% VSW I N G
Clock Outputs
20% tR tF
20%
OUTPUT SKEW
OUTPUT RISE/FALL TIME
Phase Noise Plot
Noise Power
nQ0, nQ1 Q0, Q1
Pulse Width t
PERIOD
Phase Noise Mask
odc =
f1 Offset Frequency f2
t PW t PERIOD
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
8422004AGI
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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REV. A MARCH 29, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8422004I
FEMTOCLOCKSTMLVCMOS/CRYSTAL-TOLVHSTL FREQUENCY SYNTHESIZER APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS8422004I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VDDA.
3.3V or 2.5V VDD .01F VDDA .01F 10F 10
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS8422004I has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using a 26.5625MHz 18pF parallel resonant crystal and were chosen to minimize the ppm error.
XTAL_OUT C1 22p X1 18pF Parallel Crystal XTAL_IN C2 22p
ICS8422004I
Figure 2. CRYSTAL INPUt INTERFACE
8422004AGI
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REV. A MARCH 29, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8422004I
FEMTOCLOCKSTMLVCMOS/CRYSTAL-TOLVHSTL FREQUENCY SYNTHESIZER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8422004I. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS8422004I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 100mA = 346.5mW Power (outputs)MAX = 32.8mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 32.8mW = 131.2mW
Total Power_MAX (3.465V, with all outputs switching) = 346.5mW + 131.2mW = 477.7mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 65C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.478W * 65C/W = 99.85C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE JA
FOR
24-PIN TSSOP, FORCED CONVECTION
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 70C/W
1
65C/W
2.5
62C/W
8422004AGI
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REV. A MARCH 29, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8422004I
FEMTOCLOCKSTMLVCMOS/CRYSTAL-TOLVHSTL FREQUENCY SYNTHESIZER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load. HSTL output driver circuit and termination are shown in Figure 3.
VDDO
Q1
VOUT RL 50
FIGURE 3. HSTL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load.
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.
Pd_H = (V
OH_MAX
/R ) * (V
L DD_MAX
-V
OH_MAX
) )
Pd_L = (V
OL_MAX
/R ) * (V
L DD_MAX
-V
OL_MAX
Pd_H = (1V/50) * (2V - 1V) = 20mW Pd_L = (0.4V/50) * (2V - 0.4V) = 12.8mW Total Power Dissipation per output pair = Pd_H + Pd_L = 32.8mW
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REV. A MARCH 29, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8422004I
FEMTOCLOCKSTMLVCMOS/CRYSTAL-TOLVHSTL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE
FOR
24 LEAD TSSOP
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 70C/W
1
65C/W
2.5
62C/W
TRANSISTOR COUNT
The transistor count for ICS8422004I is: 2951
8422004AGI
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REV. A MARCH 29, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8422004I
FEMTOCLOCKSTMLVCMOS/CRYSTAL-TOLVHSTL FREQUENCY SYNTHESIZER
24 LEAD TSSOP
PACKAGE OUTLINE - G SUFFIX
FOR
TABLE 8. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 7.70 6.40 BASIC 4.50 Millimeters Minimum 24 1.20 0.15 1.05 0.30 0.20 7.90 Maximum
Reference Document: JEDEC Publication 95, MO-153
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REV. A MARCH 29, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8422004I
FEMTOCLOCKSTMLVCMOS/CRYSTAL-TOLVHSTL FREQUENCY SYNTHESIZER
Marking ICS8422004AGI ICS8422004AGI Package 24 Lead TSSOP 24 Lead TSSOP Shipping Packaging tube 2500 tape & reel Temperature -40C to 85C -40C to 85C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS8422004AGI ICS8422004AGIT
The aforementioned trademark, HiPerClockSTM and FEMTOCLOCKSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8422004AGI
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